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NM34C02 2K-Bit Standard 2-Wire Bus Interface
March 1999
NM34C02 2K-Bit Standard 2-Wire Bus Interface
Designed with Permanent Write-Protection for First 128 Bytes for Serial Presence Detect Application on Memory Modules Features General Description
The NM34C02 is 2048 bits of CMOS non-volatile electrically erasable memory. It is designed to support Serial Presence Detect circuitry in memory modules. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s). The contents of the non-volatile memory allows the CPU to determine the capacity of the module and the electrical characteristics of the memory devices it contains. This will enable "plug and play" capability as the module is read and PC main memory resources utilized through the memory controller. The first 128 bytes of the memory of the NM34C02 can be permanently Write Protected by writing to the "WRITE PROTECT" Register. Write Protect implementation details are described under the section titled Addressing the WP Register. The NM34C02 is available in a JEDEC standard TSSOP package for low profile memory modules for systems requiring efficient space utilization such as in a notebook computer. Two options are available: L - Low Voltage and LZ - Low Power, allowing the part to be used in systems where battery life is of primary importance. s Extended Operating Voltage: 2.7V-5.5V s Write-Protection for first 128 bytes s 200 A active current typical - 10 A standby current typical - 1.0 A standby current typical (L) - 0.1 A standby current typical (LZ) s IIC compatible interface - Provides bidirectional data transfer protocol s Sixteen byte page write mode - Minimizes total write time per byte s Self timed write cycle - Typical write cycle time of 6ms s Endurance: 1,000,000 data changes s Data retention greater than 40 years s Packages available: 8-pin TSSOP and 8-pin SO
Block Diagram
VCC VSS START CYCLE SDA START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR LOAD A2 A1 A0 WORD ADDRESS COUNTER INC 16 XDEC E2PROM ARRAY 16 x 16 x 8 H.V. GENERATION TIMING &CONTROL
SCL
0/1/2/3 4 4
16
R/W
YDEC
Device Address Bits Write Protect Register CK DIN
8 DOUT
DATA REGISTER
DS012821-1
(c) 1999 Fairchild Semiconductor Corporation NM34C02 Rev. D.2
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NM34C02 2K-Bit Standard 2-Wire Bus Interface
Connection Diagram
SO (M8) and TSSOP (MT8) Package
A0 A1 A2 VSS 1 2 3 4 8 VCC NC SCL SDA
DS012821-2
NM34C02
7 6 5
Top View See Package Number M08A and MTC08
Pin Names
A0,A1,A2 VSS SDA SCL NC VCC Device Address Inputs Ground Data I/O Clock Input No Connection Power Supply
Ordering Information NM34C02 XX X X
Package M8 = 8 pin SOIC MT8 = 8 pin TSSOP Temperature Range Blank = 0C to +70C E = -40C to +85C Voltage Range Blank = 4.5V to 5.5V L = 2.7V to 4.5V LZ = 2.7V to 4.5V and < 1A standby current Device 2K IIC Serial EEPROM
DS012821-21
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NM34C02 2K-Bit Standard 2-Wire Bus Interface
Product Specifications Absolute Maximum Ratings
Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 seconds) ESD Rating -65C to +150C 6.5V to -0.3V +300C 2000V min.
Operating Conditions
Ambient Operating Temperature NM34C02 NM34C02E Positive Power Supply NM34C02 NM34C02L NM34C02LZ 0C to +70C -40C to +85C 4.5V to 5.5V 2.7V to 4.5V 2.7V to 4.5V
Standard VCC (4.5V to 5.5V) DC Electrical Characteristics
Symbol Parameter Test Conditions Min
ICCA ISB ILI ILO VIL VIH VOL Active Power Supply Current Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage IOL = 3 mA fSCL = 100 kHz VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC -0.3 VCC x 0.7
Limits Typ (Note 1)
0.2 10 0.1 0.1
Units Max
1.0 50 1 1 VCC x 0.3 VCC + 0.5 0.4 mA A A A V V V
Low VCC (2.7V to 5.5V) DC Electrical Characteristics
Symbol Parameter Test Conditions Min
ICCA ISB ILI ILO VIL VIH VOL Active Power Supply Current Standby Current for L Standby Current for LZ Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage IOL = 3 mA fSCL = 100 kHz VIN = GND or VCC VIN = GND or VCC VIN = GND to VCC VOUT = GND to VCC -0.3 VCC x 0.7
Limits Typ (Note 1)
0.2 1 0.1 0.1 0.1
Units Max
1.0 10 1 1 1 VCC x 0.3 VCC + 0.5 0.4 mA A A A A V V V
Capacitance TA = +25C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol
CI/O CIN
Test
Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL)
Conditions
VI/O = 0V VIN = 0V
Max
8 6
Units
pF pF
Note 1: Typical values are TA = 25C and nominal supply voltage (5V). Note 2: This parameter is periodically sampled and not 100% tested.
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NM34C02 2K-Bit Standard 2-Wire Bus Interface
AC Conditions of Test
Input Pulse Levels Input Rise and Fall Times Input & Output Timing Levels Output Load VCC x 0.1 to VCC x 0.9 10 ns VCC x 0.5 1 TTL Gate and CL = 100 pF
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 4.5V)
Symbol
fSCL TI
Parameter
SCL Clock Frequency Noise Suppression Time Constant at SCL, SDA Inputs (Minimum VIN Pulse width) SCL Low to SDA Data Out Valid Time the Bus Must Be Free before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time - NM34C02 - NM34C02L, NM34C02LZ
100 KHz Min Max
100 100 0.3 4.7 4.0 4.7 4.0 4.7 0 250 1 300 4.7 300 10 15 3.5
400 KHz Min Max
400 50 0.1 1.3 0.6 1.5 0.6 0.6 0 100 0.3 300 0.6 50 10 15 0.9
Units
KHz ns s s s s s s s ns s ns s ns ms
tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tWR (Note 3)
Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the NM34C02 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
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NM34C02 2K-Bit Standard 2-Wire Bus Interface
Bus Timing
tF tHIGH tLOW SCL tLOW tR
SDA
SDA
OUT
Background Information (IIC Bus)
As mentioned, the IIC bus allows synchronous bidirectional communication between Transmitter/Receiver using the SCL (clock) and SDA (Data I/O) lines. All communication must be started with a valid START condition, concluded with a STOP condition and acknowledged by the Receiver with an ACKNOWLEDGE condition. In addition, since the IIC bus is designed to support other devices such as RAM, EPROMs, etc., a device type identifier string must follow the START condition. For EEPROMs, this 4-bit string is 1010. Also refer the Addressing the WP Register section. As shown below, although the EEPROMs on the IIC bus may be configured in any manner required, the total memory addressed can not exceed 16K (16,384 bits) on the Standard IIC protocol. EEPROM memory address programming is controlled by 2 methods: * Hardware configuring the A0, A1, and A2 pins (Device Address pins) with pull-up or pull-down resistors. All unused pins must be grounded (tied to VSS). * Software addressing the required PAGE BLOCK within the device memory array (as sent in the Slave Address string). Addressing an EEPROM memory location involves sending a command string with the following information: [DEVICE TYPE]--[DEVICE ADDRESS]--[PAGE BLOCK ADDRESS]--[BYTE ADDRESS]
,,
tSU:STA tHD:STA IN
tHD:DAT
tSU:DAT
tSU:STO
tBUF tDH
tAA
DS012821-4
DEFINITIONS
BYTE PAGE 8 bits of data 16 sequential addresses (one byte each) that may be programmed during a 'Page Write' programming cycle 2,048 (2K) bits organized into 16 pages of addressable memory. (8 bits) x (16 bytes) x (16 pages) = 2,048 bits Any IIC device CONTROLLING the transfer of data (such as a microprocessor) Device being controlled (EEPROMs are always considered Slaves) Device currently SENDING data on the bus (may be either a Master or Slave). Device currently receiving data on the bus (Master or Slave)
PAGE BLOCK
MASTER
SLAVE TRANSMITTER
RECEIVER
Example of 16K of Memory on 2-Wire Bus
VCC
SDA SCL
VCC VCC VCC VCC
NM34C02L
A0 A1 A2 VSS
NM24C02
A0 A1 A2 VSS
NM24C04
A0 A1 A2 VSS
NM24C08
A0 A1 A2 VSS
To VCC or VSS
To VCC or VSS
To VCC or VSS
To VCC or VSS
DS012821-5
Note:
The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state. It is recommended that the total line capacitance be less than 400pF. Specific timing and addressing considerations are described in greater detail in the following sections.
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NM34C02 Rev. D.2
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NM34C02 2K-Bit Standard 2-Wire Bus Interface
Device
NM34C02
Address Pins A0 A1 A2
ADR ADR ADR
Memory Size
2048 Bits
Number of Page Blocks
1
Pin Descriptions
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the device.
Start Condition
All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The NM34C02 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs.
Stop Condition
All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the NM34C02 to place the device in the standby power mode.
Device Operation Inputs (A0, A1, A2)
Device address pins A0, A1, and A2 are connected to VCC or VSS to configure the EEPROM chip address. Table A shows the active pins across the NM34C02 device family.
ACKNOWLEDGE
Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line to LOW to acknowledge that it received the eight bits of data. Refer to Figure 3. The NM34C02 device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the NM34C02 will respond with an acknowledge after the receipt of each subsequent eight bit byte. In the Read mode the NM34C02 slave will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode.
Table 1.
Device NM34C02L A0 A1 A2 Effects of Addresses 8 devices max.
ADR ADR ADR
Device Operation
The NM34C02 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is the master and the device that is controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the NM34C02 will be considered a slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2.
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NM34C02 2K-Bit Standard 2-Wire Bus Interface
Write Cycle Timing
SCL
SDA
8th BIT WORD n
ACK tWR STOP CONDITION START CONDITION
DS012821-6
SCL
DATA STABLE
DATA CHANGE
SDA
DS012821-7
Data Validity (Figure 1).
SCL START CONDITION SDA STOP CONDITION
Start and Stop Definition (Figure 2).
DS012821-8
SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START
1
8
9
ACKNOWLEDGE
Acknowledge Responses from Receiver (Figure 3).
DS012821-9
Device Addressing
Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are those of the device type identifier (see Figure 4). This is fixed as 1010 for all EEPROM devices. All IIC EEPROMs use an internal protocol that defines a PAGE BLOCK size of 2K bits (for Byte addresses 00 through FF).
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NM34C02 Rev. D.2
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NM34C02 2K-Bit Standard 2-Wire Bus Interface
Device Addressing (Continued)
Device Type Identifier Device Address
instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to fifteen more bytes. After the receipt of each byte, the NM34C02 will respond with an acknowledge.
R/W (LSB)
DS012821-10
1
0
1
0
A2
A1
A0
NM34C02
Slave Addresses (Figure 4).
Refer to the following table for Slave Address string details:
Device
NM34C02
A0
A
A1
A
A2
A
Page Blocks
1 (2K)
Page Block Addresses
(None)
After the receipt of each byte, the internal address counter increments to the next address and the next SDA data is accepted. If the master should transmit more than sixteen bytes prior to generating the stop condition, the address counter will 'roll over' and the previously written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowledge, and data transfer sequence.
Acknowledge Polling
Once the stop condition is issued to indicate the end of the host's write operation the NM34C02 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the NM34C02 is still busy with the write operation no ACK will be returned. If the NM34C02 has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation.
Write Operations
The last bit of the slave address defines whether a write or read condition is requested by the master. A '1' indicates that a read operation is to be executed, and a '0' initiates the write mode. A simple review: After the NM34C02 recognizes the start condition, the devices interfaced to the IIC bus wait for a slave address to be transmitted over the SDA line. If the transmitted slave address matches an address of one of the devices, the designated slave pulls the line LOW with an acknowledge signal and awaits further transmissions.
Software Write Protect
Write protection on the NM34C02 protects the first 128 bytes of the EEPROM memory. Write protection is implemented through a seperate register called the WRITE PROTECT (WP) Register and writing to this WP register permanently WRITE protects the memory. This WP register is a "one-time-only-write" register. Once this register is written, it cannot be erased. After the first WRITE to this register, all future access' to this register are ignored as if an invalid IIC cycle occured. To write protect, the user must perform a byte write to the WP register. This will permanently disable programming to the first 128 bytes of memory.
Byte Write
For a write operation a second address field is required which is a byte address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page block of memory. Upon receipt of the byte address the NM34C02 responds with an acknowledge and waits for the next eight bits of data, again, responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the NM34C02 begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the NM34C02 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.
Addressing the WP Register
Addressing the WP register is very similar to accessing any memory array with the following difference: Instead of the conventional "1010" IIC device address, the unused IIC device address "0110" is used to access just the WP register. Device address "1010" will be used for all the typical memory array access. With this difference in place, accessing the WP register is same as a typical IIC byte write cycle as described under "Write Operations" section. All timing information and waveform details remain the same. The "Byte Address" and the "Data" fields of the Byte write cycle serve as place holders and can be of any value (Don't Care). Refer to Figure 7.
Page Write
The NM34C02 is capable of a sixteen byte page write operation. It is initiated in the same manner as the byte write operation; but
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NM34C02 2K-Bit Standard 2-Wire Bus Interface
Write Protect Scheme (Continued)
Bus Activity: Master SDA Line A C K A C K A C K
DS012821-14
S T A R T
SLAVE ADDRESS
WORD ADDRESS
DATA
S T O P
Byte Write (Figure 5).
S T A R T S T O P
Bus Activity: Master SDA Line
SLAVE ADDRESS
BYTE ADDRESS (n)
DATA n
DATA n + 1
DATA n + 15
A C K
A C K
A C K
A C K
A C K
DS012821-15
Page Write (Figure 6).
S T A R T S T O P
Bus Activity: Master SDA Line Bus Activity:
SLAVE ADDRESS
BYTE ADDRESS
DATA
DEVICE ADDRESS
A C K
DON'T CARE
A C K
DON'T CARE
A C K
DS012821-16
WP Register Write (Figure 7).
Read Operations
Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read, and sequential read. slave address, R/W bit set to zero, and then the word address to be read. After the Slave word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the NM34C02 and then by the eight bit word. The master will not acknowledge the transfer but does generate the stop condition, and therefore the NM34C02 discontinues transmission. Refer to Figure 9 for the address, acknowledge and data transfer sequence.
CURRENT ADDRESS READ
Internally the NM34C02 contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. Upon receipt of the slave address with R/W set to one, the NM34C02 issues an acknowledge and transmits the data byte. The master will not acknowledge the transfer but does generate a stop condition, and therefore the NM34C02 discontinues transmission. Refer to Figure 8 for the sequence of address, acknowledge and data transfer.
SEQUENTIAL READ
Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The NM34C02 continues to output data for each acknowledge received. The read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. The data output is sequential, with the data from address n followed by the data from n + 1. The address counter for read
RANDOM READ
Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition,
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NM34C02 2K-Bit Standard 2-Wire Bus Interface
Read Operations (Continued)
operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. After the entire memory has been read, the counter 'rolls over' and the NM34C02 continues to output data for each acknowledge received. Refer to Figure 10 for the address, acknowledge, and data transfer sequence.
S T A R T
Bus Activity: Master SDA Line
SLAVE ADDRESS
S T O P
A C K
DATA
DS012821-17
Current Address Read (Figure 8).
S T A R T S T A R T S A C K A C K A C K DATA n
DS012821-18
Bus Activity: Master SDA Line
SLAVE ADDRESS
BYTE ADDRESS
SLAVE ADDRESS
S T O P
Random Read (Figure 9).
S T O P
Bus Activity: Master SDA Line
Slave Address
A C K
A C K
A C K
A C K
Data n
Data n +1
Data n + 2
Data n + x
DS012821-19
Sequential Read (Figure 10).
VCC
SDA SCL Master Transmitter/ Receiver
Note:
Slave Receiver
Slave Transmitter/ Receiver
Master Transmitter
Master Transmitter/ Receiver
DS012821-20
Due to open drain configuration of SDA, a bus-level resistor is called for (Typical value = 4.7)
Typical System Configuration (Figure 11).
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NM34C02 Rev. D.2
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NM34C02 2K-Bit Standard 2-Wire Bus Interface
Physical Dimensions inches (millimeters) unless otherwise noted
0.189 - 0.197 (4.800 - 5.004)
8765
0.228 - 0.244 (5.791 - 6.198)
1234
Lead #1 IDENT 0.150 - 0.157 (3.810 - 3.988) 8 Max, Typ. All leads 0.04 (0.102) All lead tips
0.010 - 0.020 x 45 (0.254 - 0.508)
0.053 - 0.069 (1.346 - 1.753)
0.004 - 0.010 (0.102 - 0.254) Seating Plane
0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads
0.016 - 0.050 (0.406 - 1.270) Typ. All Leads
0.014 (0.356) 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508)
8-Pin Molded Small Outline Package (M8) Order Number NM34C02LM8/LZM8 Package Number M08A
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NM34C02 Rev. D.2
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NM34C02 2K-Bit Standard 2-Wire Bus Interface
Physical Dimensions inches (millimeters) unless otherwise noted
0.114 - 0.122 (2.90 - 3.10)
8
5
(4.16) Typ (7.72) Typ 0.169 - 0.177 (4.30 - 4.50) (1.78) Typ (0.42) Typ (0.65) Typ
0.246 - 0.256 (6.25 - 6.5)
0.123 - 0.128 (3.13 - 3.30)
1
4
Pin #1 IDENT
Land pattern recommendation
0.0433 Max (1.1) 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) Typ.
See detail A
0.0035 - 0.0079
0.0075 - 0.0098 (0.19 - 0.30)
0-8
Gage plane
DETAIL A Typ. Scale: 40X
0.020 - 0.028 (0.50 - 0.70) Seating plane
0.0075 - 0.0098 (0.19 - 0.25)
Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93
8-Pin Molded TSSOP, JEDEC (MT8) Order Number NM34C02LMT8/LZMT8 Package Number MTC08
Life Support Policy
Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Francais Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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